High-speed digital interface testing, DDR testing

DDR – double data rate memory

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DDR memory testing

As is usually the case with a high-speed serial data bus, oscilloscopes can handle virtually all of the requirements for testing double data rate (DDR) data transfers and signal properties, both during development and for DDR compliance testing. At the physical layer, network analyzers can provide the highest level of accuracy for signal integrity testing. It is critical for manufacturers of computers and all types of electronic devices that use Random Access Memory (RAM) to run programs, as well as for memory chip suppliers throughout the industry to conduct a DDR memory test during design and later for functional DDR verification and production quality control.

DDR basics

DDR technology for transferring memory to and from a processor was introduced in 1998 and is now in its fifth generation. DDR stands for “double” data rate; because there are two memory transfers per clock cycle. Previously, there was only one, so DDR quickly replaced SDRAM, or Synchronous Dynamic Random Access Memory. DDR now dominates read/write memory access for all types of small processors and computers. With each generation of DDR, data transfer rates and clock frequency have increased, while operating voltages and power consumption have decreased. The huge increase in performance and the lack of backward compatibility between generations means that multiple generations of DDR are in common use – from DDR5, introduced in top-end PCs in 2021, back to DDR2, introduced in 2003. While DDR2 components are still sold in large quantities because there are many processors using the technology, new development is strictly limited.

Webinar: DDR memory system design verification and debug

Your DDR challenges

DDR versions are not compatible; you need to choose which version is most suitable for a particular project; in all likelihood sometimes one DDR version will be better suited than another.
DDR is bi-directional; how do you determine whether data is being written to or read from memory?
Test equipment budget is limited; which test equipment best meets your needs and your budget?
DDR Compliance testing consists of a series of procedures that must be strictly adhered to, if the results are to be valid; you need to be sure you are conducting compliance tests correctly.
The higher the frequency, the greater the signal loss effects of the probes, cables, and adapters. For measurements to be meaningful, the influences of the test setup need to be accounted for.

Our DDR testing solutions

Both R&S®RTO64 and R&S®RTP oscilloscopes provide the required performance for conducting DDR3 and DDR4 memory tests. Dedicated DDR options for both oscilloscopes are unique on the market for supporting triggering on and decoding DDR signals, and testing compliance to the official JEDEC specifications of the DDR standards.

Most of the problems facing designers of circuits including memory read-write functions using a DDR interface will be in the board layout; issues such as inadequate bandwidth, cross-coupling from other functional blocks, mismatches in impedance, or jitter. Both oscilloscope families include a wide range of functions for debugging poor performance in terms of signal integrity and content, and verifying performance, such as fast statistical measurements, real-time eye, advanced jitter decomposition, and more.

The bandwidth of the oscilloscope is the most significant factor for determining which signals can be acquired, and for which test purpose. For debug the bandwidth should cover the 3rd harmonic of the fundamental frequency of the required signal, for compliance test the 5th harmonic.

DDR3 (1.5v), DDR3L (1.35v), and LPDDR3 (1.2v), and require option K91 on an R&S®RTO64 or R&S®RTP.
For DDR3 bandwidths up to 1.6 GHz an R&S®RTO64 with 4 GHz bandwidth is more than adequate, higher bandwidths up to the 2.133 GHz DDR3 maximum requires 6 GHz bandwidth, or an R&S®RTP. Using an R&S®RTP084, easily investigate up to the fifth harmonic of the maximum DDR3 bandwidth, for both design debug and compliance test.
DDR4 or LPDDR4 require option K93 and an 8 GHz R&S®RTP084. To verify the rise times on the data and control signals, an R&S®RTP164 may be more suitable.

To simplify and automate compliance procedures with either of these options, the R&S®ScopeSuite provides:

The comprehensive Graphical Wizard to guide through the compliance procedures from beginning to end.
Automated control of all necessary oscilloscope settings and compliance test sequences.
Most competitors use post-processing to de-embed (correct for) the setup effects, the R&S®RTP in contrast uses digital filters (option K122). Compensate for setup equipment in real time, up to the maximum million per second update rate, a factor of hundreds faster than competitors
Configurable test reports to document the test results.

Rohde & Schwarz also supplies all the necessary accessories such as highspeed probes with the high impedance required for the high bandwidth, single end bus, and test fixtures for DDR debug, signal integrity testing, validation and compliance testing.

For interface testing between DDR modules and PCB, Rohde & Schwarz network analyzers (R&S®ZNA, R&S®ZNB) provide signal integrity measurements with a dynamic range and maximum bandwidth that comfortably exceeds all DDR requirements. For both analyzer families, option K2 plus K20 provides time domain analysis including eye diagrams and simultaneous frequency domain analysis.

Advanced probing in DDR3/DDR4 memory design

When testing designs with DDR memories, it is equally important to look into the measurement techniques as well as the probing solutions. Selecting the right probe, probing at the right place, modifying probe tip impedance to compensate interposer resistors and improving the measurement accuracy through deembedding are important to achieve repeatable and accurate test results.

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System verification and debug of DDR3/4 memory designs

DDR memory technology
common design challenges
verification and debug strategies
typical measurements

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Efficient eye diagram testing in DDR3/DDR4 system designs

When debugging DDR SI issues, tools like mask test, eye diagram and read/write separation are needed to facilitate the analysis effort. The R&S®RTx-K91 (DDR3/DDR3L/LPDDR3) and R&S®RTx-K93 (DDR4/ LPDDR4) options offer the full tool chain, from DDR system validation and debug to compliance test.

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Triggering read and write cycles of DDR3 memories

Reliably separating read/write cycles is crucial for analyzing the signal integrity of DDR memory interfaces. The R&S®RTP oscilloscope's digital trigger and zone trigger provide versatile and flexible triggering capabilities for tests on DDR memory interfaces.

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Real-time deembedding with the R&S®RTP

It is necessary to deembed the interposer characteristics to get measurement results at the BGA interface of the DDR memory device. With the R&S®RTP-K122 option, the R&S®RTP offers real-time deembedding to measure and trigger on deembedded signals in real time.

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Optimizing differential measurements on high-speed interfaces

The R&S®RT-ZM modular probe system offers measurements in differential mode and common mode as well as single-ended measurements. The ground connection prevents the circuit from floating and ensures stable and reproducible signals.

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Enhancing channel-to-channel alignment for accurate multichannel acquisition

Measurement and alignment of channel-to-channel skew is an important prerequisite, when doing accurate multichannel measurements. R&S®RTO and R&S®RTP oscilloscopes provide an optional high-speed differential pulse source (R&S®RTO-B7 and R&S®RTP-B7) to facilitate this alignment.

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